To form a semiconductor device, a multitude of elements are formed on or near a surface layer of a semiconductor substrate and electrically connected with each other through conductive lines. Accordingly, there is need for each element formed in a narrow region on the substrate to be electrically isolated from adjacent elements such that the elements are not electrically influenced by each other. For this, in the semiconductor device, an isolation layer or isolation structure is commonly used.
However, as the degree to which semiconductor devices are integrated continues to increase and a size of the various elements is minimized to reduce a distance between the elements or increase a density of the elements, it becomes increasingly difficult to exclude inter-element interference.
To solve the aforementioned problems, a fabrication technique has been developed that uses an SOI substrate in which a buried oxide layer is formed below the device elements. Particularly, in a high performance semiconductor device such as a central processing unit (CPU), the SOI type semiconductor device in which an element region is completely isolated by an insulation layer is widely used. Deep trench isolation techniques are frequently employed to isolate device elements laterally.
Formation of deep trench isolation can be partially accomplished with low-cost dielectric films. Low-cost dielectric films typically have less desirable electrical characteristics (e.g., dielectric breakdown strength or higher shrinkage values) than a high-quality film. However, due to their increased cost (either in terms of material used for their production and/or processing techniques required for their formation and deposition), high-quality films are unsuitable for filling the deep trench.
A high-quality dielectric film is a better choice for filling shallow trench isolation (STI) regions and for producing cap layers over a deep trench fill layer. However, when both types of fill are present in a structure, only one film, preferably the high-quality film, should be exposed at the surface. If both film types are exposed, one of the two films will likely have a higher etch rate during subsequent cleaning and etching processes.
With a differential etch rate, vertical steps typically appear. The vertical steps frequently cause polysilicon stringers to form during a subsequent polysilicon deposition process step. Polysilicon stringers are thin “strings” of polysilicon left along any steps or gaps on an uppermost surface topography of the substrate after etching operations. These stringers occur because the thickness of the polysilicon film is much thicker at a step or gap than in flat areas, by approximately the step height plus the polysilicon thickness. Overetching the polysilicon film to eliminate stringers is undesirable since (1) increased costs result from added or prolonged fabrication steps or operations; and (2) required conductive features may also be etched away. The polysilicon stringers can result in electrical shorts between adjacent polysilicon conductors on a surface of the composite dielectric film. The electrical shorts can produce catastrophic failures in one or more active devices on an integrated circuit (IC) chip, consequently leading to low fabrication yield.